1. Field of the Invention
Embodiments of the present invention generally relate to generating chip layout designs. More particularly, embodiments of the present invention relate to generating the padring layout design.
2. Related Art
Typically, the integrated circuit (or chip) design process begins with a specification which describes the functionality of the chip and may include a variety of constraints. Then, during a logic design phase, the logical implementation of the integrated circuit is determined. Several operations are performed to obtain a logical representation of the integrated circuit. Generally, EDA software tools use register transfer logic (RTL) to represent the integrated circuit. However, additional EDA software tools may be used.
After completing the logic design phase, the chip undergoes a physical layout design phase. Typically, the output of the logic design phase is a netlist, which is then used in the physical layout design phase. Here, EDA software tools layout the integrated circuit to obtain a layout representation of the physical components in the integrated circuit, whereas the layout representation indicates the manner in which the integrated circuit will be fabricated on a semiconductor wafer. A variety of operations are performed on the layout of the integrated circuit.
At the end of the physical layout design phase, the final layout representation of the semiconductor chip (in which the integrated circuit is implemented is sent to a semiconductor manufacturing plant. Typically, the semiconductor chip is fabricated and then coupled to a package, whereas an electrical coupling is established between the padring of the semiconductor chip and the package.
During the physical layout design phase, the padring layout design is generated. The padring is an area where differing electrical, timing, physical, and logical views of the physical layout design come together. In particular, the padring is an interface for input signals, output signals, power signals, and ground signals between a semiconductor chip and off-chip components. FIG. 1 illustrates a conventional padring layout design 10. When combined with the trend of increasing pin counts, fast clocks, and tight design schedules, the complexity of generating the padring layout design can be overwhelming. In order to satisfy this variety of constraints, a high level of control in partitioning, placement, and routing the various aspects of the padring layout design is required. This is often done by hand and can be a laborious process that does not lend itself to making changes in a repeatable manner.
Moreover, laying out a padring with a high pin count, fast clock, low skew, and/or tight design schedule is a daunting task that can occupy a designer for months. The sheer amount of details that must be tracked and incorporated into the padring layout design is a management task in and of itself. Figuring out a pinout that will route in the package and still satisfy the constraints on the die (or chip) involves knowledge in many areas. High clock rates and tight skew requirements demand precision and regularity in the layout of I/O cells and associated routes in the padring. Considerations dealing with the die such as the distance from the core of the die to the I/O area in the padring can disclose the fact that the distance is often too far to guarantee timing. On the package side, the layout of the bumps/bond pads in the padring has to be coordinated with the package to deliver a system that works together. Last minute changes and design schedule pressure can help this problem become a nightmare unless a systematic approach is used.